FIG. 1 is a block diagram showing the outline of the configuration of a conventional semiconductor memory device. As seen from FIG. 1, in this semiconductor memory device, an address A.sub.R /A.sub.r (=A.sub.1R /A.sub.IR .about.A.sub.XR /A.sub.XR) is inputted to a row decoder RD. The row decoder RD selects one of word lines WL.sub.1 to WL.sub.s (S=2.sup.x). Further, a single column decoder CD2 to which addresses A.sub.(N+1)C to A.sub.MC are inputted selects one of P (=2.sup.M-N) column decoders CD1, CD1, . . . . Addresses A.sub.1C /A.sub.1C to A.sub.NC /A.sub.NC are inputted to respective column decoders CD1. Each column decoder CD1 selects one of 2.sup.N column blocks CB in the main section MP. Each column block CB includes n columns C. n data can be inputted to the column block CB and outputted therefrom at the same time. Each column block has so called a column specification of x n bits and 2.sup.N columns. In each column block CB, the memory cell MC is composed of s N-channel MOS transistors Q.sub.1, Q.sub.2, . . . , and s N-channel MOS capacitors C1, C2, . . . connected to the respective transistors. These transistors are connected to one of respective bit line pairs BL and NBL and respective word lines WL. n-pairs of bit lines BL1, NBL1; BL2, NBL2; . . . are connected to n sense amplifiers SA1, SA2, . . . , respectively. n sense amplifiers SA1, SA2, . . . are connected to n pairs of input lines I 01, NI 01; I 02, NI 02; . . . through n pairs of N-channel MOS transistors Qp1, Qp2, . . . , Qn1, Qn2, . . . , respectively. n-pairs of input lines I 01, NI 01; I 02, NI 02; . . . are connected to n input drivers ID1, ID2, . . . , and n data D1, D2, . . . are inputted from the respective drivers. On the other hand, column decoders CD1 for control are connected in parallel with the gates of n pairs of transistors, i.e., e.g., the gates of transistors Qp1 and Qn1, the gates of transistors Qp2 and Qn2, the gates of transistors Qp3 and Qn3, the gates of transistors Qp4 and Qn4, and the like, respectively. Namely, n columns in one column block CB are simultaneously selected by an output from the decoder CD1.
WI/01, WI/02, . . . denote input/output pins, respectively.
In the above-mentioned device, writing of data into the memory cell is carried out as follows. Namely, n data D1, D2, . . . are delivered to n input drivers IOD1, IOD2, . . . , respectively. Further, column addresses A.sub.1C /A.sub.1C to A.sub.NC /A.sub.NC are delivered to the respective column decoders CD1. In addition, column addresses A.sub.(N+1)C /A.sub.1C to A.sub.NC /A.sub.NC are delivered to the column decoder CD2. Thus, it is possible to write, one by one, n data D1, D2, . . . into respective n columns by the single access. Namely, n write data D1, D2, . . . are delivered to n pairs of input lines I/01, NI/01; I/02, NI/02; . . . through n input buffers (input drivers) IOD1, IOD2, . . . . These data are delivered to one of n pairs of bit lines BL1, NBL1; BL2, NBL2; . . . through n sense amplifiers SA1, SA2, . . . from one of n pairs of transistors Qp1, Qn1; Qp2, Qn2; . . . each functioning as a transfer gate. As a result, n data D1, D2, . . . are simultaneously written, one by one, into n capacitors (cells) C1, C2, . . . through n transistors Q.sub.1, Q.sub.2, . . . by the single access.
In the case of using the semiconductor memory device as constructed above as an image memory, there are many instances where a high speed write cycle using an ordinary write cycle, or a page mode, etc. is used in reading data into the memory. In this case, the number of data which can be written by the single access is n which is the same as the number of input drivers IOD1, IOD2, . . .
Since the conventional semiconductor memory device is constructed as above, it has drawbacks as described below. Namely, only an extremely small quantity of data can be written by a single access. For this reason, the conventional semiconductor memory device is not suitable for use as an image memory. Namely, since the quantity of write data is small, and the processing speed is low in the case of the above-mentioned conventional memory device even if an attempt is made to satisfy various processing, e.g., painting-out function or color display function, etc., it is difficult to cope with such a requirement.